AMD Geode SC2200 manuals

Amd Geode SC2200 User Manual (429 pages)

Brand: Amd | Category: Hardware | Size: 3.28 MB |

English

Table of contents

AMD Geode™ SC2200 Processor

1

Data Book

1

Contents

3

List of Figures

5

List of Tables

10

1.0Overview

13

1.2 Features

14

Overview

16

2.0Architecture Overview

17

2.2 Video Processor Module

22

2.3 Core Logic Module

23

2.4 SuperI/O Module

23

2.5.1 Reset Logic

24

3.0Signal Definitions

25

Signal Definitions

26

3.1 Ball Assignments

27

SC2200 Processor

28

3.2 Strap Options

43

3.4 Signal Descriptions

48

3.4.9 IDE Interface Signals

59

3.4.16 GPIO Interface Signals

66

(Continued)

69

Reserved - RSVD

78

4.3 WATCHDOG

79

4.3.2 WATCHDOG Registers

80

4.4 High-Resolution Timer

81

4.5 Clock Generators and PLLs

83

Circuitry

84

Default ADL Multiplier

85

0111 33.33 4 0100 133

85

4.5.4 SuperI/O Clocks

86

4.5.6 Video Processor Clocks

86

4.5.7 Clock Registers

87

5.0SuperI/O Module

89

5.1 Features

90

5.2 Module Architecture

91

5.3.4 Address Decoding

93

Configuration

98

SuperI/O Module

100

5.5 Real-Time Clock (RTC)

105

5.5.3 RTC Registers

111

Table 5-19. RTC Register Map

111

Table 5-20. RTC Registers

111

Table 5-25. Extended RAM Map

115

Table 5-24. Standard RAM Map

115

5.6.1 Event Detection

116

Type Name

117

Type Name

117

5.7 ACCESS.bus Interface

121

5.7.3 Acknowledge (ACK) Cycle

122

5.7.6 Arbitration on the Bus

123

5.7.7 Master Mode

123

5.7.8 Slave Mode

125

5.7.9 Configuration

125

5.8 Legacy Functional Blocks

129

Offset Name

130

404h EDR Data Bits

130

Architecture

131

Table 5-43. Bank 1 Bit Map

134

Table 5-44. Bank 2 Bit Map

134

Table 5-45. Bank 3 Bit Map

134

Port 3 (SP3) Functionality

135

Table 5-56. Bank 1 Bit Map

139

Table 5-57. Bank 2 Bit Map

139

Table 5-58. Bank 3 Bit Map

139

Table 5-59. Bank 4 Bit Map

139

Table 5-60. Bank 5 Bit Map

140

Table 5-61. Bank 6 Bit Map

140

Table 5-62. Bank 7 Bit Map

140

6.0Core Logic Module

141

6.2 Module Architecture

142

6.2.2 PSERIAL Interface

143

6.2.3 IDE Controller

144

Core Logic Module

146

6.2.4 Universal Serial Bus

147

6.2.5 Sub-ISA Bus Interface

147

6.2.6 AT Compatibility Logic

152

Figure 6-7. PIT Timer

154

6.2.8 Keyboard Support

157

C1 Power State - Active Idle

158

Sleep States

160

6.2.11 GPIO Interface

167

6.2.12 Integrated Audio

167

AMD Geode™

170

Processor

170

SMI# (System Management

171

Read to Clear

172

Figure 6-15. Typical Setup

173

Table 6-12. Cycle Types

174

6.3 Register Descriptions

175

6.3.2 Register Summary

176

6.4 Chipset Register Space

190

CPI mode

202

. Reads as 0

220

20h and 24h)

221

1), this bit allows signal

230

Not Used Reset Value: 00h

244

. Must be set to 0

252

0 Reserved. (Read Only)

260

Not Used

269

: X-Bus Expansion Registers

278

00h/02h[14]

278

Reserved Reset Value = xxh

291

7.0Video Processor Module

307

7.1 Module Architecture

308

7.2 Functional Description

309

(Not normally User Data)

310

Figure 7-4. VIP Block Diagram

311

Video Processor Module

312

7.2.2 Video Block

315

7.2.3 Mixer/Blender Block

318

Windows Configuration

321

7.2.5 Integrated DACs

323

7.2.6 TFT Interface

324

crystal oscilla

325

7.3 Register Descriptions

326

8.0Debugging and Monitoring

349

Debugging and Monitoring

350

9.0Electrical Specifications

351

9.1.4 Operating Conditions

352

9.1.5 DC Current

353

Electrical Specifications

354

9.2 DC Characteristics

358

9.3 AC Characteristics

363

GX1 Processor Series Data

365

9.3.2 Video Port

367

9.3.3 CRT and TFT Interface

368

9.3.4 ACCESS.bus Interface

370

Note 2. t

371

Ω1 KΩ 10 pF

373

Figure 9-18. PCI Reset Timing

378

9.3.6 Sub-ISA Interface

379

9.3.7 LPC Interface

383

9.3.8 IDE Interface

384

9.3.11 Fast IR Port

407

9.3.13 Audio Interface (AC97)

412

9.3.14 Power Management

417

9.3.15 Power-Up Sequencing

418

9.3.16 JTAG Interface

420

10.0Package Specifications

423

Figure 10-1. Heatsink Example

424

10.2 Physical Dimensions

425

Package Specifications

426

A.1 Order Information

427

Table A-1. Revision History

428

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