AMD HD8650WCGHBOX Datasheet download pdf (Page 37)

Product Errata 37

Revision Guide for AMD Family 10h Processors

41322 Rev. 3.16 February 2008

295 DRAM Phy Configuration Access Failures

Description

Under a highly specific set of asynchronous timing conditions established during cold boot (S5 to S0

transition) or resume (S4 or S3 to S0 transition), the skew between the DRAM controllers (DCTs) and

DRAM phy may lead to unreliable communication for DRAM phy configuration accesses.

Potential Effect on System

The system may hang during DRAM configuration accesses when using DCT link ganged mode

([DRAM Controller Select Low Register] F2x110[DctGangEn] = 1b), or fail DRAM training in link

ganged mode or in link unganged mode.

Suggested Workaround

Contact your AMD representative for information on a BIOS update.

Fix Planned

Yes

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AMD HD8650WCGHBOX Datasheet Page 37