AMD Duron User Manual Page 45
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Chapter 7 Signal and Power-Up Requirements 33
23802E—September 2000 AMD Duron™ Processor Data Sheet
Preliminary Information
Timing Requirements. The signal timing requirements are as
follows:
1. RESET# must be asserted before PWROK is asserted
The AMD Duron processor does not set the correct clock
multiplier if PWROK is asserted prior to a RESET#
assertion. It is recommended that RESET# be asserted at
least 10ns
prior to the assertion of PWROK.
2. All motherboard power supplies should be ramped before
the assertion of PWROK.
The processor core voltage, VCC_CORE, should have a
stable voltage (for example, 1.7V) as indicated by the
Voltage ID (VID) prior to PWROK assertion. Before PWROK
assertion, the AMD Duron processor is clocked by a ring
oscillator. This minimum time is not specified.
The AMD Duron processor PLL is powered by VCCA. The
processor PLL does not lock if VCCA is not high enough for
the processor logic to switch for some period before PWROK
is asserted. The recommended minimum time before
PWROK assertion is 5
µs.
3. The system clock (SYSCLK/SYSCLK#) should be running
before PWROK is asserted.
When PWROK is asserted, the AMD Duron processor
switches from driving the internal processor clock grid from
the ring oscillator to driving from the PLL. The reference
system clock should be valid at this time. If it is not valid,
the subsequent requirements may be undermined. It is
recommended that PWROK be asserted 3ms after the
system clocks are running.
4. PWROK assertion to deassertion of RESET#
The duration of reset during cold boots is intended to
satisfy the time it takes for the PLL to lock with a less than
1-ns phase error. The AMD Duron processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.5ms.
5. PWROK should be monotonic.
The processor should not switch between the ring oscillator
and the PLL after the initial assertion of PWROK.
- AMD Duron 1
- Contents 3
- Contents v 5
- List of Figures 7
- List of Tables 9
- Preliminary Information 10
- Revision History 11
- 1 Overview 13
- 23802E—September 2000 14
- 4 Overview Chapter 1 16
- 2 Interface Signals 17
- 2.3 Push-Pull (PP) Drivers 18
- 2.4 AMD System Bus Signals 18
- 3 Logic Symbol Diagram 19
- 4 Power Management 21
- CLKFWDRST 26
- 5 Thermal Design 29
- 18 Thermal Design Chapter 5 30
- 6 Electrical Data 31
- VCCA-NOISE 33
- 6.8 Absolute Ratings 34
- 6.9 Power Dissipation 34
- = 400mV V 35
- 24 Electrical Data Chapter 6 36
- Figure 9. SYSCLK Waveform 36
- SKEW-SAMEEDGE 38
- SKEW-DIFFEDGE 38
- Chapter 6 Electrical Data 29 41
- 30 Electrical Data Chapter 6 42
- 7.1 Power-Up Requirements 43
- 8 Mechanical Data 49
- 38 Mechanical Data Chapter 8 50
- Measurements are in mm 51
- 40 Mechanical Data Chapter 8 52
- 9 Pin Descriptions 53
- AMD Duron™ Processor 54
- Topside View 54
- Chapter 9 Pin Descriptions 43 55
- 44 Pin Descriptions Chapter 9 56
- Chapter 9 Pin Descriptions 45 57
- 46 Pin Descriptions Chapter 9 58
- Chapter 9 Pin Descriptions 47 59
- 48 Pin Descriptions Chapter 9 60
- 9.2 Pin List 61
- 50 Pin Descriptions Chapter 9 62
- Chapter 9 Pin Descriptions 51 63
- 52 Pin Descriptions Chapter 9 64
- Chapter 9 Pin Descriptions 53 65
- 54 Pin Descriptions Chapter 9 66
- Chapter 9 Pin Descriptions 55 67
- 56 Pin Descriptions Chapter 9 68
- 9.3 Detailed Pin Descriptions 69
- 64 Pin Descriptions Chapter 9 76
- 10 Ordering Information 77
- Appendix A 79
- Conventions, Abbreviations 79
- Data Terminology 80
- Abbreviations and Acronyms 81
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