AMD Duron User Manual download pdf (Page 74)

62 Pin Descriptions Chapter 9

AMD Duron™ Processor Data Sheet 23802E—September 2000

Preliminary Information

the AMD Duron processor. These voltage ID values are defined

inTable 21.

Note: The VID[3:0] for Slot A has a different code definition than

VID[4:0] for Socket A.

For more information, see the “Required Circuits” chapter of

the Motherboard PGA Design Guide, order# 90009.

VREFSYS Pin VREFSYS (W5) drives the threshold voltage for the system bus

input receivers. VREFSYS is set to 0.5 * VCC_CORE. In

addition, to minimize VCC_CORE noise rejection from

VREFSYS, include decoupling capacitors. For more

information, see the Motherboard PGA Design Guide, order#

90009.

ZN, VCC_Z, ZP, and

VSS_Z Pins

ZN (AC5), VCC_Z (AC7), ZP (AE5), and VSS_Z (AE7) are the

push-pull compensation circuit pins. VCC_Z is tied to

VCC_CORE. VSS_Z is tied to VSS.

If Push-Pull mode is selected by the SIP parameter SysPushPull

asserted (SysPushPull=1), ZN is tied to VCC_CORE with a

Table 21. VID[4:0] Code to Voltage Definition

VID[4:0] VCC_CORE (V) VID[4:0] VCC_CORE (V)

00000 1.850 10000 1.450

00001 1.825 10001 1.425

00010 1.800 10010 1.400

00011 1.775 10011 1.375

00100 1.750 10100 1.350

00101 1.725 10101 1.325

00110 1.700 10110 1.300

00111 1.675 10111 1.275

01000 1.650 11000 1.250

01001 1.625 11001 1.225

01010 1.600 11010 1.200

01011 1.575 11011 1.175

01100 1.550 11100 1.150

01101 1.525 11101 1.125

01110 1.500 11110 1.100

01111 1.475 11111 No CPU

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 83 84

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AMD Duron User Manual Page 74