Amd Geode SC2200 User Manual Page 28
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28 AMD Geode™ SC2200 Processor Data Book
Signal Definitions
32580B
Figure 3-2. BGU481 Ball Assignment Diagram
S
SS
SS
SSS
S
12345678910111213141516171819202122232425262728293031
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
Note: Signal names have been abbreviated in this figure due to space constraints.
V
SS
V
IO
AD30 PCK0 REQ1# PRST# PCICK IOW# GP20 GP17 HSNC AV
CCCT
V
SS
GREEN BLUE V
SS
V
PLL2
PD7 V
SS
PD6 PD1 STB# NC NC NC D+P3 D-P3 D+P1 D-P1 V
IO
V
SS
12345678910111213141516171819202122232425262728293031
V
SS
V
IO
AD29 AD28 REQ0# AD23 V
SS
RD# WR# V
SS
VSNC RED V
IO
AV
SSCT
STRES V
IO
BUSY ACK# V
IO
SLIN# INIT# V
SS
NC V
SS
V
SS
NC D+P2 D-P2 GP10 V
SS
V
IO
AD26 AD24 V
IO
AD25 GNT0# GNT1# V
IO
RMCS# GP19 V
IO
IRTX V
SSCT
AV
CCCT
AV
SSCT
AV
SSCT
AV
SSP2
SLCT PD4 PD5 PD3 PD0 V
IO
NC NC V
IO
INTB# AV
SSUSB
GP9 V
IO
GP7 GP8
AD21 AD22 AD20 AD27 AD31 PCK1 V
SS
FRM# IOR# GP1 TRDE # V
CCCT
V
SS
V
IO
AV
CCCT
VREF PE V
IO
V
SS
PD2 ERR# AFD# V
IO
NC V
SS
INTA# AV
CCUSB
GP6 SOUT TDP TDN
AD16 AD19 AD18 DVSL# SIN2 TRST# TDO TCK
TRDY# IRDY# CBE2# AD17
TMS TDI GTST VPCKI
STOP# V
SS
V
IO
V
SS
V
SS
V
IO
V
SS
VPD7
SRR# PRR# LOCK# CBE3#
VPD6 VPD5 VPD4 VPD3
AD13 CBE1# AD15 PAR
VPD2 VPD1 VPD0 GP39
AD11 V
IO
V
SS
AD14 GP38 V
IO
V
SS
GP37
CBE0# AD9 AD10 AD12
GP36 GP35 GP34 GP33
V
SS
AD7 V
IO
AD8
GP32 GP13 V
IO
V
SS
AD3 AD6 AD5 V
SS
AD4 ICS1# AD1 V
CORE
V
SS
GP12 AB1D AB1C
V
CORE
SDO SYNC ACCK
V
SS
V
SS
V
SS
V
SS
V
CORE
V
CORE
V
CORE
V
CORE
AD0 IAD2 AD2 V
CORE
IDAT15 IDAT14 IDAT13 V
SS
V
IO
V
SS
IDAT 12 IDAT11
IDAT10 IDAT9 IDAT8 IIOR0#
IRST# IDAT7 IDAT6 IDAT5
IDAT4 V
SS
V
IO
IDAT3
IDAT1 IDAT2 IDAT0 IDRQ0
IIORY0 IIOW0# IAD0 IDACK0#
IAD1 V
SS
V
IO
V
SS
IRQ14 ICS0# SOUT1 OVRCUR#
GP18 SIN1 X27I TEST1
V
SS
V
SS
V
SS
V
SS
V
CORE
V
CORE
V
CORE
V
CORE
V
CORE
ACRST# BITCK SDI
V
SS
SDCK3 GXCK GP16
MD57 SDCK1 V
SS
V
IO
MD58 MD59 MD60 MD56
SDCK2 MD61 MD62 MD63
MD24 V
IO
V
SS
DQM7
MD25 MD26 MD27 DQM3
MD52 MD29 MD30 MD31
V
SS
V
IO
V
SS
MD28
MD50 MD49 MD54 MD53
MD21 DQM6 DQM2 MD55
PWRE X27O TEST0 V
IO
PBTN# GPW0 V
SS
CK32 POR# MD3 MD5 WEA# V
SS
V
IO
MA1 MD34 MD37 V
IO
V
SS
MD41 MA9 MA8 DQM1 MD13 V
SS
MA11 CS1# MD18 MD48 MD20 MD51
TEST2 X32I X32O V
PLL3
ONCT# GPW2 V
IO
GP11 MD0 V
IO
MD6 CASA# BA0 MA10 MD32 MD33 MD36 MD47 MD45 MD42 SDCK0 V
IO
MA6 MA3 V
IO
MD11 SDCKI MD19 V
IO
MD22 MD17
V
IO
V
SS
AV
SSP3
THRM# GPW1 PCNT1 V
SS
IRRX1 MD1 V
SS
MD7 RASA# V
IO
BA1 MA2 V
IO
MD35 MD46 V
IO
MD43 DQM5 V
SS
MA5 MD15 V
SS
MD14 MD12 SDCKO MD16 V
SS
V
IO
V
SS
V
IO
V
BAT
LED# V
SB
V
SBL
PCNT2 SDATI2 MD2 MD4 DQM0 CS0# V
SS
MA0 DQM4 V
SS
MD38 MD39 V
SS
MD44 MD40 CKEA MA7 MA4 MD8 MD10 MD9 MA12 MD23 V
IO
V
SS
S
= GND Ball
= PWR Ball
= Strap Option Ball
= Multiplexed Ball
S
V
CORE
V
CORE
V
SS
V
SS
V
SS
V
CORE
V
CORE
V
CORE
V
CORE
V
SS
V
SS
V
SS
V
CORE
V
CORE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
CORE
V
CORE
V
SS
V
SS
V
SS
V
CORE
V
CORE
V
CORE
V
CORE
V
SS
V
SS
V
SS
V
CORE
V
CORE
(Top View)
AMD Geode™
SC2200 Processor
- AMD Geode™ SC2200 Processor 1
- Data Book 1
- Contents 3
- List of Figures 5
- List of Tables 10
- 1.0Overview 13
- 1.2 Features 14
- Overview 16
- 2.0Architecture Overview 17
- 2.2 Video Processor Module 22
- 2.3 Core Logic Module 23
- 2.4 SuperI/O Module 23
- 2.5.1 Reset Logic 24
- 3.0Signal Definitions 25
- Signal Definitions 26
- 3.1 Ball Assignments 27
- SC2200 Processor 28
- 3.2 Strap Options 43
- 3.4 Signal Descriptions 48
- 3.4.9 IDE Interface Signals 59
- 3.4.16 GPIO Interface Signals 66
- (Continued) 69
- Reserved - RSVD 78
- 4.3 WATCHDOG 79
- 4.3.2 WATCHDOG Registers 80
- 4.4 High-Resolution Timer 81
- 4.5 Clock Generators and PLLs 83
- Circuitry 84
- Default ADL Multiplier 85
- 0111 33.33 4 0100 133 85
- 4.5.4 SuperI/O Clocks 86
- 4.5.6 Video Processor Clocks 86
- 4.5.7 Clock Registers 87
- 5.0SuperI/O Module 89
- 5.1 Features 90
- 5.2 Module Architecture 91
- 5.3.4 Address Decoding 93
- Configuration 98
- SuperI/O Module 100
- 5.5 Real-Time Clock (RTC) 105
- 5.5.3 RTC Registers 111
- Table 5-19. RTC Register Map 111
- Table 5-20. RTC Registers 111
- Table 5-25. Extended RAM Map 115
- Table 5-24. Standard RAM Map 115
- 5.6.1 Event Detection 116
- Type Name 117
- Type Name 117
- 5.7 ACCESS.bus Interface 121
- 5.7.3 Acknowledge (ACK) Cycle 122
- 5.7.6 Arbitration on the Bus 123
- 5.7.7 Master Mode 123
- 5.7.8 Slave Mode 125
- 5.7.9 Configuration 125
- 5.8 Legacy Functional Blocks 129
- Offset Name 130
- 404h EDR Data Bits 130
- Architecture 131
- Table 5-43. Bank 1 Bit Map 134
- Table 5-44. Bank 2 Bit Map 134
- Table 5-45. Bank 3 Bit Map 134
- Port 3 (SP3) Functionality 135
- Table 5-56. Bank 1 Bit Map 139
- Table 5-57. Bank 2 Bit Map 139
- Table 5-58. Bank 3 Bit Map 139
- Table 5-59. Bank 4 Bit Map 139
- Table 5-60. Bank 5 Bit Map 140
- Table 5-61. Bank 6 Bit Map 140
- Table 5-62. Bank 7 Bit Map 140
- 6.0Core Logic Module 141
- 6.2 Module Architecture 142
- 6.2.2 PSERIAL Interface 143
- 6.2.3 IDE Controller 144
- Core Logic Module 146
- 6.2.4 Universal Serial Bus 147
- 6.2.5 Sub-ISA Bus Interface 147
- 6.2.6 AT Compatibility Logic 152
- Figure 6-7. PIT Timer 154
- 6.2.8 Keyboard Support 157
- C1 Power State - Active Idle 158
- Sleep States 160
- 6.2.11 GPIO Interface 167
- 6.2.12 Integrated Audio 167
- AMD Geode™ 170
- Processor 170
- SMI# (System Management 171
- Read to Clear 172
- Figure 6-15. Typical Setup 173
- Table 6-12. Cycle Types 174
- 6.3 Register Descriptions 175
- 6.3.2 Register Summary 176
- 6.4 Chipset Register Space 190
- CPI mode 202
- . Reads as 0 220
- 20h and 24h) 221
- 1), this bit allows signal 230
- Not Used Reset Value: 00h 244
- . Must be set to 0 252
- 0 Reserved. (Read Only) 260
- Not Used 269
- : X-Bus Expansion Registers 278
- 00h/02h[14] 278
- Reserved Reset Value = xxh 291
- 7.0Video Processor Module 307
- 7.1 Module Architecture 308
- 7.2 Functional Description 309
- (Not normally User Data) 310
- Figure 7-4. VIP Block Diagram 311
- Video Processor Module 312
- 7.2.2 Video Block 315
- 7.2.3 Mixer/Blender Block 318
- Windows Configuration 321
- 7.2.5 Integrated DACs 323
- 7.2.6 TFT Interface 324
- crystal oscilla 325
- 7.3 Register Descriptions 326
- 8.0Debugging and Monitoring 349
- Debugging and Monitoring 350
- 9.0Electrical Specifications 351
- 9.1.4 Operating Conditions 352
- 9.1.5 DC Current 353
- Electrical Specifications 354
- 9.2 DC Characteristics 358
- 9.3 AC Characteristics 363
- GX1 Processor Series Data 365
- 9.3.2 Video Port 367
- 9.3.3 CRT and TFT Interface 368
- 9.3.4 ACCESS.bus Interface 370
- Note 2. t 371
- Ω1 KΩ 10 pF 373
- Figure 9-18. PCI Reset Timing 378
- 9.3.6 Sub-ISA Interface 379
- 9.3.7 LPC Interface 383
- 9.3.8 IDE Interface 384
- 9.3.11 Fast IR Port 407
- 9.3.13 Audio Interface (AC97) 412
- 9.3.14 Power Management 417
- 9.3.15 Power-Up Sequencing 418
- 9.3.16 JTAG Interface 420
- 10.0Package Specifications 423
- Figure 10-1. Heatsink Example 424
- 10.2 Physical Dimensions 425
- Package Specifications 426
- A.1 Order Information 427
- Table A-1. Revision History 428
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