AMD Athlon 6 Specifications Page 16

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16 Product Errata
25759 Rev. 3.79 July 2009
Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
135 INVLPG Instruction With Address Prefix Does Not
Correctly Invalidate the Translation Requested
X XXXXXXX
136 INVLPG Instruction in 16-bit Mode May Not
Invalidate the Translation Requested
X XXXXXXX
147 Potential Violation of Read Ordering Rules
Between Semaphore Operations and Unlocked
Read-Modify-Write Instructions
XXX X XXX X
153 Potential System Hang in Multiprocessor Systems
With 14 Cores
XXX X X X X X
154 Incorrect Diode Offset X
156 Read Request Incorrectly Generated for Invalid
GART Page Table Entries
No fix planned
161 Performance-Monitoring Counters Do Not Count
Code Address Matches
X XXXXXXX
166 FXSAVE/FXRSTOR Instructions Use 64-bit Format
in Compatibility Mode
XXXXX X XXXXXXX
169 System May Hang Due to DMA or Stalled Probe
Response
No fix planned
181 Asserting LDTSTOP_L Before DRAM is Initialized
May Cause System Hang
XXXXX X XXXXXXX
312 CVTSD2SS and CVTPD2PS Instructions May Not
Round to Zero
No fix planned
352 SYSCALL Instruction May Execute Incorrectly Due
to Breakpoint
No fix planned
353 SYSRET Instruction May Execute Incorrectly Due
to Breakpoint
No fix planned
393 Performance Monitor May Count Fastpath Double
Operation Instructions Incorrectly
No fix planned
Table 5. Cross-Reference of Product Revision to Errata (Continued)
No. Errata Description
Revision Number
SH-B3
SH-C0
SH-CG
DH-CG
CH-CG
SH-D0
DH-D0
CH-D0
JH-E1
DH-E3
SH-E4
BH-E4
SH-E5
DH-E6
JH-E6
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