AMD Athlon 6 Specifications download pdf (Page 67)

Product Errata 67

Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors

25759 Rev. 3.79 July 2009

107 Possible Multiprocessor Coherency Problem with Setting Page

Table A/D Bits

Description

In a multiprocessor system, a coherency failure may occur in a situation involving a TLB refill, an L1

fill, an L1 victim write, and an external probe, when all four addresses match as described in the

following sequence:

1. A TLB miss occurs which requires the state of the page A (accessed) or D (Dirty) bit in one of the

associated page map entries.

2. The cache line containing the page map entry must hit in the L2.

3. A younger load or store misses both in the data cache (DC) and L2 causing a DC line fill.

4. The DC fill generates an L1 victim.

5. The L1 victim is in the modified state.

6. The L1 fill matches the L1 index (11:6) of the TLB reload but not the L2 index [15:6, 14:6, or

13:6 for 1M, 512K, 256K] of the cache line containing the above page map entry.

7. The LRU bit for the L2 index points to the way (1 of 16) containing the page map entry.

8. The L1 victim arrives at the L2 in a small window after the TLB reload read, but before the write

of the A/D bit(s).

9. An external probe arrives for the same address as the page map entry.

Potential Effect on System

In the unlikely event that the above conditions occur, multiprocessor memory coherency issues may

occur leading to unpredictable system failure. This erratum has not been observed outside of a highly

randomized synthetic stress test.

Suggested Workaround

BIOS should set BUCFG.ThrL2IdxCmpDis (bit 43) to one.

Fix Planned

Yes

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AMD Athlon 6 Specifications Page 67