AMD Athlon 6 Specifications download pdf (Page 22)

22 Product Errata

25759 Rev. 3.79 July 2009

Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors

52 Short LDTSTOP_L Deassertion Can Result in Elevated

Processor Core Voltage

Description

While in a low power mode with LDTSTOP_L asserted, if LDTSTOP_L is deasserted and quickly

reasserted before the HyperTransport™ links have reinitialized, then an erroneous (elevated) voltage

encoding may be driven out on the VID pins.

The erroneous VID code is the intended core voltage for the current processor performance state, plus

the programmed Ramp VID Offset from the Clock Power/Timing High register (Dev:3xD8[30:28]).

Potential Effect on System

The processor core remains in the elevated voltage condition that was intended only for the short

period while the internal clock was ramping. This voltage stays in affect until the next processor

performance state transition is performed by software.

Suggested Workaround

When deasserting LDTSTOP_L, do not reassert it until the links have reinitialized.

Fix Planned

Yes

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AMD Athlon 6 Specifications Page 22