AMD K5 User Manual download pdf (Page 17)

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

unit can operate independently, other units can continue exe-

cution when one or more units are stalled. A 16-entry reorder

buffer keeps track of the original instruction sequence and

ensures that the results are retired in program order.

4.3 Register Renaming

The x86 architecture has only eight general-purpose registers.

This significantly increases register reuse (loads and stores)

and register dependencies. The register reuse is addressed

with multiple load/store execution units and a dual-ported data

cache. The AMD-K5 processor uses register renaming to over-

come register dependencies. Multiple logical registers for each

physical register allow execution units to use the same physi-

cal name registers simultaneously.

4.4 64-Bit Data Bus Interface Unit

The AMD-K5 processor uses a 64-bit data bus that provides

higher throughput and support for 64-bit data paths, and a

cache/burst-oriented line refill for loading the processor’s

internal separate instruction and data caches. As code and

data enter the bus interface unit, the internal cache refills con-

tinually as fast as five clock cycles per cache line. The

enhanced bandwidth of the processor’s data bus and the con-

tinuous cache refill process reduces processing delays and sup-

ports superior processor and overall system performance.

4.5 Innovative x86 Instruction Predecoding

While processing variable-length instructions is manageable in

single-issue 4th-generation and dual-issue 5th-generation

CPUs, only the AMD-K5 processor employs the necessary inno-

vative techniques to issue as many as four x86 instructions per

clock cycle.

Every byte of code that enters the AMD-K5 processor is tagged

with associated predecode information that identifies the x86

instruction boundaries and enables multiple x86 instructions

(varying in length from 8 to 120 bits) to be aligned. Once

aligned, the instructions are assigned issue positions for the

most efficient instruction processing

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contributing to the pro-

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AMD K5 User Manual Page 17