AMD K5 User Manual download pdf (Page 46)

AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

Instruction Cache

Coherency

The instruction cache protocol is a subset of the data cache

protocol where only Invalid and Shared states are imple-

mented. Read hits provide the data to the processor. Read

misses result in a read allocate operation that loads the line

into the cache and the data is provided to the processor. The

first data is provided as soon as it arrives from memory.

Write cycles are never generated to the instruction cache, but

inquire cycles may hit in the instruction cache, resulting in the

cache line being invalidated.

Self-Modifying Code

and the Cache

A snoop write hit to the instruction cache is treated as self-

modifying code. The cache line is invalidated and all instruc-

tions in the instruction pipeline are flushed. Execution restarts

at the instruction following the one causing the snoop. This

guarantees exact execution of cacheable self-modifying code.

For non-cacheable code, a jump should be placed between the

modification of the code and its execution.

8.5 External Bus Description

The AMD-K5 processor external bus is identical to the P54C

64-bit bus, and will run at 1.5x or 2.0x multiples of the external

bus frequency. The bus state transitions are illustrated in

Figure 4.

Table 10. Inquire Cycles to Data Cache

State INV Next State Note

0 S Snoop hit to modified line:

Assert HIT and HITM, Write back modified data to

memory, Negate HITM, Transition cache state when

complete.

Snoop hit to unmodified line:

Assert HIT, Transition cache state

Snoop hit to unmodified line:

Assert HIT

, Transition cache state

I x I Snoop miss: Negate HIT

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 99 100

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AMD K5 User Manual Page 46