AMD K5 User Manual download pdf (Page 35)

100

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

CLK Clock PEN Synchronous Note 4

EADS

Synchronous RESET Asynchronous

EWBE

Synchronous Note 4 R/S Asynchronous

FLUSH

Asynchronous SMI Asynchronous

FRCMC

Asynchronous Note 2 STPCLK Asynchronous

HOLD Synchronous WB/WT

Synchronous Note 6

Table 2. Output Pins

Name Floated At (Note 1) Name Floated At (Note 1)

A4–A3 Bus Hold, Address Hold, BOFF

HLDA Always Driven

ADS

Bus Hold, BOFF IERR Always Driven

ADSC

Bus Hold, BOFF LOCK Bus Hold, BOFF

APCHK Always Driven M/IO Bus Hold, BOFF

BE7–BE0 Bus Hold, BOFF PCD Bus Hold, BOFF

BREQ Always Driven PCHK Always Driven

CACHE

Bus Hold, BOFF PRDY Always Driven

D/C

Bus Hold, BOFF PWT Bus Hold, BOFF

FERR Always Driven SCYC LOCK not asserted, Bus Hold, BOFF

HIT Always Driven SMIACT Always Driven

HITM

Always Driven W/R Bus Hold, BOFF

Notes:

1. All outputs float during Tri-State test mode.

Table 1. Input Pins (continued)

Name Type Note Name Type Note

Notes:

1. A20M may change during RESET or during a serializing event like an I/O write. A state change at other times will result in incorrect

address generation on subsequent memory cycles.

2. BF and FRCMC

are normally connected to V

or V

by a jumper. For correct operation, any change on these signals should be

followed by a RESET.

3. BUSCHK

is sampled in every clock. Any asserted sample is remembered and takes effect on the same clock as the last BRDY.

4. These are sampled in the same clock as BRDY.

5. This is sampled in the same clock as EADS.

6. These are sampled with the first BRDY

or NA and must meet setup to every clock

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