AMD K5 User Manual download pdf (Page 48)

AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

Memory objects can be 8, 16, 32, or 64 bits. I/O objects are 8,

16, or 32 bits. Both appear as fields on the 64-bit data bus.

Data is transferred on the byte lines corresponding to the

address. 16-bit or 32-bit objects crossing a 32-bit boundary, or

64-bit objects crossing a 64-bit boundary, are misaligned and

will require multiple cycles to transfer.

The byte-enable signals and the data lines correspond in the

following manner:

8.6 Bus Cycles

Bus cycles encode normal read and write accesses to code or

data space and handle special events such as interrupt

acknowledge. The type of cycle is determined by the CACHE,

D/C, M/IO, and W/R outputs. The processor encodes informa-

tion with the byte-enable signals for special bus cycles. (See

Table 6 on page 27.)

If M/IO is asserted Low or PCD is driven High in any cycle,

CACHE is not asserted. The processor uses a burst transfer of

four 64-bit accesses, corresponding to the 32-byte line size of

the caches, for bus cycles involving cache line movement.

Table 11 shows the order of burst accesses expected by the

external protocol.

■ BE7: D63–D56 ■ BE3: D31–D24

■ BE6: D55–D48 ■ BE2: D23–D16

■ BE5: D47–D40 ■ BE1: D15–D8

■ BE4: D39–D32 ■ BE0: D7–D0

Table 11. Addressing of the AMD-K5 Processor Burst Order

If 1st Address = 0 then 8 then 10 then 18

If 1st Address

= 8 then 0 then 18 then 10

If 1st Address

= 10 then 18 then 0 then 8

If 1st Address

= 18 then 10 then 8 then 0

1 2 ... 43 44 45 46 47 48 49 50 51 52 53 ... 99 100

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AMD K5 User Manual Page 48