AMD K5 User Manual download pdf (Page 38)

AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

8 Processor Operation

8.1 Power-On Configuration

The AMD-K5 processor signals at reset are listed in Table 7.

8.2 Clock State

The AMD-K5 processor uses the Enhanced 486 protocol to con-

trol the clock. This protocol provides for stopping the clock

from hardware using the STPCLK control signal, or from soft-

ware using the HALT instruction. During the clock-stopped

states, cache coherency is maintained by temporarily enabling

the clock for snoop processing and recognizing HOLD/HLDA

arbitration sequences.

A state transition diagram for a stop clock state machine

implementing five clocking states—the Enhanced 486

protocol—is illustrated in Figure 3 on page 29.

Table 7. Signals at Reset

Output

State at

Reset

Output

State at

Reset

Address Float FERR

ADS

1HIT1

APCHK

1HITM1

BE7

–BE0 Undefined HLDA 0

BRDY

1 LOCK 1

BRDYC

1M/IOUndefined

BREQ 0 PCD Undefined

CACHE Undefined PCHK

D/C

Undefined PRDY 0

Data Float PWT Undefined

DP7–DP0 Float W/R

Undefined

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 99 100

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AMD K5 User Manual Page 38