AMD K5 User Manual download pdf (Page 41)

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

interrupt, or maskable interrupt), recognition of STPCLK is

delayed until the interrupt processing is complete. However,

assertion of a higher priority interrupt will not cause the Stop

Grant State to be exited.

Stop Clock Snoop

State

In this state, all internal clocks are running and an inquire

cycle is being performed. Instruction execution is disabled and

HOLD/HLDA operate normally.

Stop Clock Snoop State is entered from Halt/Auto-Power-Down

State or Stop Grant State when an inquire cycle is detected.

This is a temporary state, lasting only until the coherency oper-

ation (snoop/miss, snoop/invalidate or snoop/writeback) is com-

plete. The clock state will then return to the previous state.

(See Figure 24 on page 72.)

Stop Clock State In this state, all internal clocks are stopped, the PLL is shut

down, and all execution is disabled. If HOLD is asserted while

the clock is running, HLDA will be generated and the buses

floated. If HOLD is negated, HLDA will be negated and the

buses will be driven to their previous state without regard to

whether the clock is running. This is the lowest power state.

The Stop Clock State is entered from the Stop Grant State by

stopping the CLK. The clock state returns to Stop Grant State

when the CLK is again started. The time required to restart the

CLK and enter the Stop Clock State is approximately 1000

clock cycles.

8.3 Cache Protocol

Internal Cache The AMD-K5 processor has a 16-Kbyte dual-tagged instruction

cache with 32-byte lines and an 8-Kbyte dual-tagged data cache

of 32-byte lines. Cache lines refill in four transfer burst cycles

from memory and align along 32-byte lines.

The operating mode is software-controlled, and on-chip caches

must be enabled by software. This is accomplished by clearing

or setting the CD and NW bits of CR0.

Any area of memory can be cached. Software can prevent

areas of memory from being cached by setting the PCD bit in

the corresponding page table entry. Hardware can prevent

areas of memory from being cached through the KEN pin.

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AMD K5 User Manual Page 41