AMD Sempron 10 Specifications download pdf (Page 132)

132 Product Errata

41322 Rev. 3.84 August 2011

Revision Guide for AMD Family 10h Processors

437 L3 Cache Performance Events May Not Reliably Track

Processor Core

Description

The following L3 cache performance events may increment for events caused by cores that are not

being tracked and may not increment for events caused by cores that are being tracked.

• F4x1C8 L3 Hit Statistics Register.

• EventSelect 4E0h Read Request to L3 Cache when the unit mask is not Fxh.

• EventSelect 4E1h L3 Cache Misses when the unit mask is not Fxh.

• EventSelect 4E2h L3 Fills caused by L2 Evictions when the unit mask is not Fxh.

• EventSelect 4EDh Non-cancelled L3 Read Requests when the unit mask is not Fxh.

Potential Effect on System

Performance monitoring software may not have an accurate count of the L3 cache accesses caused by

a specific program.

Suggested Workaround

No workaround exists for F4x1C8. For other performance events, software should use the unit mask

setting of Fxh. This setting selects all processor cores. There is no method to track the L3 cache

accesses from a single core.

Fix Planned

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AMD Sempron 10 Specifications Page 132