AMD Sempron 10 Specifications download pdf (Page 97)

Product Errata 97

Revision Guide for AMD Family 10h Processors

41322 Rev. 3.84 August 2011

370 DRAM Read Errors May Occur at DDR2-800 Memory Speeds

With Higher Read DQS Delays

Description

The processor DRAM interface may miss a beat of data under conditions of back-to-back read bursts

to the same chip select using DDR2-800 memory speeds, resulting in incorrect data read by the

DRAM interface until a processor reset occurs. This issue is sensitive to higher levels of jitter on the

read DQS inputs from DRAM in combination with higher settings of DRAM Read DQS Timing

Control [High:Low] Registers[RdDqsTimeByte][7:0] at offsets F2x[1, 0]9C_x[3:0]0[6:5].

Potential Effect on System

For systems without ECC, undefined system behavior that usually results in a system hang due to a

triple fault. Systems with ECC enabled may experience repeated multiple-bit ECC errors.

Suggested Workaround

If the system DRAM speed is DDR2-800, system software should constrain the settings of F2x[1,

0]9C_x[3:0]0[6:5][RdDqsTimeByte][7:0] obtained from DRAM training to values of 0Ch or less.

Implementation of this workaround may have a nominal effect on DDR2-800 memory margins.

Fix Planned

Yes

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AMD Sempron 10 Specifications Page 97