AMD Sempron 10 Specifications Page 31

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Product Errata 31
Revision Guide for AMD Family 10h Processors
41322 Rev. 3.84 August 2011
279 HyperTransport™ Link RTT and RON Specification Violations X
280 Time Stamp Counter May Yield An Incorrect Value X X X
293 Memory Instability After PWROK Assertion X X
295 DRAM Phy Configuration Access Failures X X
297 Single Machine Check Error May Report Overflow No fix planned
298 L2 Eviction May Occur During Processor Operation To Set
Accessed or Dirty Bit
XX
300 Hardware Memory Clear Is Not Supported After Software
DRAM Initialization
XXX
301 Performance Counters Do Not Accurately Count MFENCE or
SFENCE Instructions
XXX
302 MWAIT Power Savings May Not Be Realized when Two or
More Cores Monitor the Same Address
XXX
308 Processor Stall in C1 Low Power State X X X
309 Processor Core May Execute Incorrect Instructions on
Concurrent L2 and Northbridge Response
XX
312 CVTSD2SS and CVTPD2PS Instructions May Not Round to
Zero
XXX
315 FST and FSTP Instructions May Calculate Operand Address in
Incorrect Mode
XXX
319Inaccurate Temperature Measurement XXXX X
322 Address and Command Fine Delay Values May Be Incorrect No fix planned
326 Misaligned Load Operation May Cause Processor Core Hang X X X
327HyperTransport Link RTT Specification Violation XXXXXXXXX
328 BIST May Report Failures on Initial Powerup X X X
336 Instruction-Based Sampling May Be Inaccurate X X X
337 CPU Instruction-Based Sampling Fields May Be Inaccurate X X X
338 Northbridge Instruction-Based Sampling Fields May Be
Inaccurate
XXX
339 APIC Timer Rollover May Be Delayed No fix planned
342SMIs That Are Not Intercepted May Disable Interrupts XXXXX
343 Eviction May Occur When Using L2 Cache as General Storage
During Boot
XXXXXXXXX
344Intermittent HyperTransport Link Training Failures XXXXXXXXX
346 System May Hang if Core Frequency is Even Divisor of
Northbridge Clock
XXXXXX
348 Processor On-die Termination Resistance is Higher than
Specification
XX
350DRAM May Fail Training on Cold Reset XXXXXXXXX
351 HyperTransport™ Technology LS2 Low-Power Mode May Not
Function Correctly
XXXXX
Table 27. Cross-Reference of Product Revision to Errata (Continued)
No. Errata Description
Revision Number
DR-BA
DR-B2
DR-B3
RB-C2
BL-C2
DA-C2
RB-C3
BL-C3
DA-C3
HY-D0
HY-D1
PH-E0
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