AMD SB600 Specifications download pdf (Page 13)

2008 Advanced Micro Devices Inc.

SB600 Programming Architecture

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 13

2.2 I/O Map

The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved,

but can be disabled in some cases. Variable ranges are configurable.

2.2.1 Fixed I/O Address Ranges

2.2.1.1 Fixed I/O Address Ranges – SB600 Proprietary Ports

I/O Address Description Enable Bit

C00h-C01h IRQ Routing Index/Data register SMBus PCI Reg64h[Bit0]

C14h PCI Error Control register SMBus PCI Reg78h[Bit4]

C50h-C51h Client Management Index /Data

registers

SMBus PCI Reg 79h[Bit3]

C52h GPM Port SMBus PCI Reg78h[Bit6]

C6Fh Flash Rom Program Enable SMBus PCI Reg78h[Bit8]

CD0h-CD1h PM2 Index/Data

CD4h-CD5h BIOS RAM Index/Data

CD6h-CD7h Power Management I/O register SMBus PCI Reg64h[Bit2] & Reg78h[Bit9]

2.2.2 Variable I/O Decode Ranges

I/O Name Description Configure Register Range Size

(Bytes)

PIO0 Programmable I/O Range 0 PM IO Reg14h & Reg15h <=16

PIO1 Programmable I/O Range 1 PM IO Reg16H & Reg17H <=16

PIO2 Programmable I/O Range 2 PM IO Reg18h & Reg19h <=16

PIO3 Programmable I/O Range 3 PM IO Reg1Ah & Reg1Bh <=16

PIO4 Programmable I/O Range 4 PM IO Reg A0h & Reg A1h <=16

PIO5 Programmable I/O Range 5 PM IO Reg A2h & Reg A3h <=16

PIO6 Programmable I/O Range 6 PM IO Reg A4h & Reg A5h <=16

PIO7 Programmable I/O Range 7 PM IO Reg A6h & Reg A7h <=16

PM1_EVT ACPI PM1a_EVT_BLK PM IO Reg20h & Reg21h 4

PM1_CNT ACPI PM1a_CNT_BLK PM IO Reg22h & Reg23h 2

PM_TMR ACPI PM_TMR_BLK PM IO Reg24h & Reg25h 4

P_BLK ACPI P_BLK PM IO Reg26h & Reg27h 6

GPE0_EVT ACPI GPE0_EVT_BLK PM IO Reg28h & Reg29h 8

SMI CMD Block * SMI Command Block PM IO Reg2Ah & Reg2Bh 2

Pma Cnt Block PMa Control Block PM IO Reg2Ch & Reg2Dh 1

Reserved Reserved PM IO Reg2Eh & Reg2Fh 1

SMBus SMBus IO Space SMBus PCI Reg90h &

RegD2h[Bit0]

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 97 98

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AMD SB600 Specifications Page 13