AMD SB600 Specifications download pdf (Page 28)

2008 Advanced Micro Devices Inc.

IDE Controller

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 28

6.2 PIO Modes

The SB600 supports IDE PIO mode 0, 1, 2, 3, and 4. For PIO mode selection, the BIOS needs to

program not only the PIO mode register, but also the PIO timing register.

6.2.1 PIO Mode

The BIOS can simply give the PIO mode number through Reg4Ah on the IDE controller.

6.2.2 PIO Timing

Two parameters determine the PIO bus-cycle timing: the command width and the recovery width.

CT (bus-cycle timing) = 30ns * ((command width + 1) + (recovery width + 1))

For each PIO mode, the command width and the recovery width must be set by the BIOS

accordingly:

PIO Mode Command Width

(In Reg40h)

Recovery Width

(In Reg40h)

0 9 9 600ns = 30 * ((9+1) + (9+1))

1 4 7 390ns = 30 * ((4+1) + (7+1))

2 3 4 270ns = 30 * ((3+1) + (4+1))

3 2 2 180ns = 30 * ((2+1) + (2+1))

4 2 0 120ns = 30 * ((2+1) + (0+1))

6.3 DMA Modes

The SB600 IDE controller can run at either the legacy (Multi-Words) DMA mode, or the Ultra-

DMA mode.

6.3.1 Legacy (Multi-Words) DMA mode

The SB600 IDE controller will run at the legacy DMA mode only when the Ultra-DMA mode is

disabled.

Two parameters determine the DMA bus-cycle timing: the command width and the recovery

width.

CT (bus-cycle timing) = 30ns * ((command width + 1) + (recovery width + 1))

For each legacy DMA mode, the command width and recovery width must be set by the BIOS

accordingly:

Legacy DMA

Mode

Command Width

(In Reg44h)

Recovery Width

(In Reg44h)

0 7 7 480ns = 30 * ((7+1) + (7+1))

1 2 1 150ns = 30 * ((2+1) + (1+1))

2 2 0 120ns = 30 * ((2+1) + (0+1))

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AMD SB600 Specifications Page 28

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