AMD SB600 Specifications download pdf (Page 16)

2008 Advanced Micro Devices Inc.

SB600 Early-POST Initialization

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 16

Field Name Bits Description

Base Address 31:11 ROM Base address. The most significant 21 bits of the base address are

defined in this field. Bits 10:0 of the base address are assumed to be zero.

Base address, therefore, is aligned at a 2K boundary.

Length 10:2 These 9 bits (0-511) define the length from 1K to 512K in increments of

1K.

Read Protect 1 When set, the memory range defined by this register is read protected.

Reading any location in the range returns FFh.

Write Protect 0 When set, the memory range defined by this register is write protected.

Writing to the range has no effect.

Example:

Protect 32K LPC ROM starting with base address FFF80000.

Base address bits 31:11 1111 1111 1111 1000 0000 0 b

Length 32K bit 10:2 = 31h = 000 0111 11 b

Read protect bit 1 = 1

Write protect bit 0 = 1

Note:

1. Registers 50h ~ 5Fh can be written once after the hardware reset. Subsequent writes to them

have no effect.

2. Setting sections of the LPC ROM to either read or write protect will not allow the ROM to be

updated by a flash programming utility. Most flash utilities write and verify ROM sectors,

and will terminate programming if verification fails due to read protect.

3.1.4 SPI ROM controller

The SPI ROM interface is a new feature added to the SB600. Refer to the AMD SB600 Register Reference

Guide for more information on this feature.

Note: The LPC ROM Read/Write Protect mentioned in the previous paragraph also applies to SPI. Two

strap pins, PCICLK0 and PCICLK1, determine the SB600 boot up from LPC ROM or SPI ROM. There is

no register status to reflect whether the current ROM interface is LPC or SPI.

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AMD SB600 Specifications Page 16