AMD SB600 Specifications download pdf (Page 24)

2008 Advanced Micro Devices Inc.

SMBus Programming

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 24

5 SMBus Programming

The SB600 SMBus (System Management Bus) complies with SMBus Specification Version 2.0.

5.1 SMBus I/O Base Address

The BIOS needs to set a valid SMBus I/O base address before enabling the SMBus Controller.

There are two places at which the BIOS is able to set the SMBus I/O base addresses: one is at PCI

Reg10h, another is at PCI Reg90h, and both are on the SMBus Controller (Bus 0, Device 14h,

Function 0).

Before the BAR register, Reg10h, is assigned automatically during PCI bus enumeration, the

BIOS needs to give a temporary SMBus I/O base address for accessing devices on the SMBus.

The SMBus controller enable bit is bit 0, register D2h, of the SMBus device (Bus 0, Device 14h,

Function 0).

The following is a sample code to enable the SMBus with a temporary I/O base address:

SMB_IO EQU 8040h

; Set SMBus I/O base address

mov dx, 0CF8h ; PCI Index Register

mov eax, 8000A090h ; Reg90h on SMBus PCI Controller

out dx, eax

mov dx, 0CFCh ; PCI Data Register

mov eax, SMB_IO ; temp SMBus I/O base address

out dx, eax

; Enable the SMBus controller

mov dx, 0CF8h ; PCI Index Register

mov eax, 8000A0D0h ; RegD0 on SMBus PCI Controller

out dx, eax

mov dx, 0CFEh ; PCI Data Register

in al, dx ; read back from RegD2h

or al, 01 ; bit0 for enabling SMBus Controller interface

out dx, al

5.2 SMBus Timing

The SMBus frequency can be adjusted using different values in an 8-bit I/O register at the

SMBus base + 0Eh location.

The SMBus frequency is set as follows:

SMBus Frequency = (Primary A-Link Clock )/(Count in index 0Eh * 4)

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AMD SB600 Specifications Page 24