AMD SB600 Specifications download pdf (Page 37)

2008 Advanced Micro Devices Inc.

APIC Programming

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 37

9 APIC Programming

With the AMD integrated chipset solution, the BIOS needs to program both the Northbridge and

the Southbridge in order to support APIC.

9.1 Northbridge APIC Enable

There are three bits in the Northbridge that the BIOS should set before enabling APIC support.

• Enable Local APIC in AMD Athlon processors. (Set bit11 in APIC_BASE MSR(001B)

• Reg4C[bit1] - This bit should be set to enable. It forces the CPU request with address

0xFECx_xxxx to the Southbridge.

• Reg4C[bit18] - This bit should be set to enable. It sets the Northbridge to accept MSI

with address 0xFEEx_xxxx from the Southbridge.

9.2 Southbridge APIC Enable

There are two bits in the Southbridge that the BIOS should set before enabling APIC support.

• Reg64[bit3] = 1 to enable the APIC function.

• Reg64[bit7] = 1 to enable the xAPIC function. It is only valid if Bit3 is being set.

9.3 IOAPIC Base Address

The IOAPIC base address can be defined at SMBus PCI Reg. 74h. The power-on default value is

FEC00000h.

Note: This register is 32-bit access only. The BIOS should not use the byte restore mechanism to

restore its value during S3 resume.

9.4 APIC IRQ Assignment

SB600 has IRQ assignments under APIC mode as follows:

• IRQ0~15 – legacy IRQ

• IRQ 16 – PCI INTA

• IRQ 17 – PCI INTB

• IRQ 18 – PCI INTC

• IRQ 19 – PCI INTD

• IRQ 20 – PCI INTE

• IRQ 21 – PCI INTF

• IRQ 22 – PCI INTG

• INT 23 – PCI INTH

• IRQ 09 – ACPI SCI

SCI is still as low-level trigger with APIC enabled.

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AMD SB600 Specifications Page 37