AMD SB600 Specifications Page 98
- Page / 98
- Table of contents
- BOOKMARKS
- AMD SB600 1
- BIOS Developer’s Guide 1
- (Public Version) 1
- Table of Contents 3
- 1 Introduction 7
- 1.3 PCI Internal Devices 10
- Introduction 11
- 2.2 I/O Map 13
- 3.1 512K/1M ROM Enable 15
- 3.1.4 SPI ROM controller 16
- 3.2 Real Time Clock (RTC) 17
- 3.3 BIOS RAM 18
- 3.4 Serial IRQ 18
- 4 PCI IRQ Routing 21
- 5 SMBus Programming 24
- SMBus Programming 26
- 6 IDE Controller 27
- 6.2 PIO Modes 28
- 6.3 DMA Modes 28
- 6.3.2 Ultra-DMA Mode 29
- 7 Serial ATA (SATA) 30
- 8 Power Management 31
- 8.3 Power Management Timers 32
- 8.4 SMI Events 32
- 8.5 C-State Break Events 34
- 8.7 Wake on Events 35
- 8.8 Sleep SMI Events 35
- Power Management 36
- 9 APIC Programming 37
- 9.5 APIC IRQ Routing 38
- 10 Watchdog Timer 39
- Watchdog Timer 40
- 11 A-Link Bridge 41
- 11.2 Programming Procedure 42
- A-Link Bridge 43
- 12.1 Initialization 44
- 13.1 CIM-SB600 Architecture 46
- 13.4.1 SBPOR Interface 51
- 13.5.2 SB POST Interface 52
- 13.6.1 Requirements 53
- 13.6.2 SB Runtime Interface 53
- 14 Sample Programs 55
- 14.2 Setup Options 56
- 14.2.3 C3 Support 57
- Sample Programs 59
- 14.3 IDE Settings 63
- 14.3.3 UDMA Mode Settings 65
- 14.3.4 IDE Channel Disable 66
- 14.3.5 IDE Channel Enable 68
- 14.5 Clock Throttling 69
- 14.6 Lid Switch 71
- 14.6.4 ACPI Programming 72
- 14.9 Sleep Trap through SMI# 87
- Appendix: Revision History 98
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