AMD SB600 Specifications download pdf (Page 31)

2008 Advanced Micro Devices Inc.

Power Management

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 31

8 Power Management

On the SB600, PM registers can be accessed through I/O ports CD6h/CD7h. Before initiating any

power management functions in the SB600, the BIOS needs to set the I/O base addresses for the

ACPI I/O register, the SMI Command Port, etc.

I/O Name Description Configure Register Range Size

(Bytes)

PM1_EVT ACPI PM1a_EVT_BLK PM IO Reg20h & Reg21h 4

PM1_CNT ACPI PM1a_CNT_BLK PM IO Reg22h & Reg23h 2

PM_TMR ACPI PM_TMR_BLK PM IO Reg24h & Reg25h 4

P_BLK ACPI P_BLK PM IO Reg26h & Reg27h 6

GPE0_EVT ACPI GPE0_EVT_BLK PM IO Reg28h & Reg29h 8

SMI CMD Block * SMI Command Block PM IO Reg2Ah & Reg2Bh 2

* Notes:

• The SMI CMD Block must be dword aligned, i.e., the least significant two bits of the address

must be zero (address[1:0] must be 00). For example, B0h, B4h, B8h, BCh, etc.

• The SMI CMD Block consists of two ports – the SMI Command Port at base address, and the

SMI Status Port at base address+1.

• The writes to the SMI Status Port will not generate an SMI. The writes to the SMI Command

Port will generate an SMI.

• The SMI Command and SMI Status ports may be written individually as 8 bit ports, or

together as a 16 bit port.

8.1 SMI Handling – EOS (PM IO Reg10h[Bit0])

Upon each SMI generation, the SB600 will clear the EOS bit automatically. At the end of the

SMI service, the BIOS needs to clear the status bit of the SMI event and re-enable the EOS;

otherwise, the SB600 will not be able to generate SMI, even if SMI events arrive.

8.2 Programmable I/Os

There are eight sets of programmable I/Os available on the SB600. The BIOS can use them for

I/O trapping, which means that an SMI will be generated if any access falls into the PIO range.

The PIO address range can be set to 2, 4, 8, and 16.

I/O Name Description Configure Register Enable Status

PIO0 Programmable I/O Range 0 PM IO Reg14h & Reg15h PM IO Reg1Ch[Bit7] PM IO Reg1Dh[Bit7]

PIO1 Programmable I/O Range 1 PM IO Reg16h & Reg17h PM IO Reg1Ch[Bit6] PM IO Reg1Dh[Bit6]

PIO2 Programmable I/O Range 2 PM IO Reg18h & Reg19h PM IO Reg1Ch[Bit5] PM IO Reg1Dh[Bit5]

PIO3 Programmable I/O Range 3 PM IO Reg1Ah & Reg1Bh PM IO Reg1Ch[Bit4] PM IO Reg1Dh[Bit4]

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AMD SB600 Specifications Page 31