AMD SB600 Specifications download pdf (Page 39)

2008 Advanced Micro Devices Inc.

Watchdog Timer

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 39

10 Watchdog Timer

To enable the watchdog timer in the SB600, the following registers must be initialized:

• Enable the watchdog timer by resetting bit 0 in PMIO register 069h.

• Set bit 3 in SMBus PCI Config (Bus 0 Device 20 Function 0) Reg 41h to enable the

watchdog decode.

• Ensure that the watchdog timer base address is set to a non zero value, typically

0FEC000F0h. The watchdog base address is set at PMIO address 6Ch-6Fh as shown in the

sample program below. (PMIO is addressed as byte index/data):

Sample Program:

mov dx,0CD6h ; PMIO index register

mov al,6Fh ; Most significant base address location

out dx,al ; Set the index to 6Fh

mov dx,0CD7h ; PMIO data register

mov al,0FEh ; Most significant base address

out dx,al

mov dx,0CD6h ; PMIO index register

mov al,6Eh ; Second significant base address location

out dx,al ; Set the index to 6Eh

mov dx,0CD7h ; PMIO data register

mov al,0C0h ; Second significant base address

out dx,al

mov dx,0CD6h ; PMIO index register

mov al,6Dh ; Third significant base address location

out dx,al ; Set the index to 6Dh

mov dx,0CD7h ; PMIO data register

mov al,00h ; Third significant base address

out dx,al

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 97 98

No comments

AMD SB600 Specifications Page 39