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IDE Controller
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 27
6 IDE Controller
The SB600 IDE controller supports Ultra ATA 33/66/100/133 modes. The IDE controller can be
configured into either the compatible mode or the native mode. Under the compatible mode, the
IDE controller will use the legacy resources.
The SB600 allows programming of the IDE timing and mode for each drive independently on
each channel.
6.1 IDE Channel Enable/Disable
Register on IDE Controller Bit Description
Reg09h 1 Primary IDE channel programmable logic enable.
Reg48h 0 Set 1 to disable the primary IDE channel.
Reg48h 8 Set 1 to disable the secondary IDE channel.
With the SB600, the BIOS must follow particular sequences to enable or disable the IDE
channels (see section 6.1.1 and 6.1.2 below for further information).
6.1.1 IDE Channel Enable
Both of the IDE channels are enabled as power-on default. To enable an IDE channel, the BIOS
must be set as follows:
1. Set the IDE channel programmable logic enable bit in Reg09h.
2. Clear the IDE channel disable bit in Reg48h to enable the IDE channel.
Note: No IDE I/O port access is allowed in between step (1) and step (2). It is recommended that
the BIOS execute step (2) immediately after step (1).
Refer to section 14.3.5 for a programming sample.
6.1.2 IDE Channel Disable
To disable an IDE channel, the BIOS must:
1. Set IDE channel programmable logic enable bit in Reg09h.
2. Set IDE channel disable bit in Reg48h to disable IDE channel.
Note: No IDE I/O port access is allowed in between step (1) and (2). It’s recommended that the
BIOS execute step (2) immediately after step (1).
Note: Secondary IDE channel should always be disabled for there is no pin out for secondary
IDE.
After the IDE disable sequence, the IDE channel programmable logic enable bit will be cleared
automatically.
Refer to section 14.3.4 for a programming sample.
- AMD SB600 1
- BIOS Developer’s Guide 1
- (Public Version) 1
- Table of Contents 3
- 1 Introduction 7
- 1.3 PCI Internal Devices 10
- Introduction 11
- 2.2 I/O Map 13
- 3.1 512K/1M ROM Enable 15
- 3.1.4 SPI ROM controller 16
- 3.2 Real Time Clock (RTC) 17
- 3.3 BIOS RAM 18
- 3.4 Serial IRQ 18
- 4 PCI IRQ Routing 21
- 5 SMBus Programming 24
- SMBus Programming 26
- 6 IDE Controller 27
- 6.2 PIO Modes 28
- 6.3 DMA Modes 28
- 6.3.2 Ultra-DMA Mode 29
- 7 Serial ATA (SATA) 30
- 8 Power Management 31
- 8.3 Power Management Timers 32
- 8.4 SMI Events 32
- 8.5 C-State Break Events 34
- 8.7 Wake on Events 35
- 8.8 Sleep SMI Events 35
- Power Management 36
- 9 APIC Programming 37
- 9.5 APIC IRQ Routing 38
- 10 Watchdog Timer 39
- Watchdog Timer 40
- 11 A-Link Bridge 41
- 11.2 Programming Procedure 42
- A-Link Bridge 43
- 12.1 Initialization 44
- 13.1 CIM-SB600 Architecture 46
- 13.4.1 SBPOR Interface 51
- 13.5.2 SB POST Interface 52
- 13.6.1 Requirements 53
- 13.6.2 SB Runtime Interface 53
- 14 Sample Programs 55
- 14.2 Setup Options 56
- 14.2.3 C3 Support 57
- Sample Programs 59
- 14.3 IDE Settings 63
- 14.3.3 UDMA Mode Settings 65
- 14.3.4 IDE Channel Disable 66
- 14.3.5 IDE Channel Enable 68
- 14.5 Clock Throttling 69
- 14.6 Lid Switch 71
- 14.6.4 ACPI Programming 72
- 14.9 Sleep Trap through SMI# 87
- Appendix: Revision History 98
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