AMD SB600 Specifications download pdf (Page 34)

2008 Advanced Micro Devices Inc.

Power Management

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 34

8.4.1 Power Button

Power button is always a wake-up event and can be programmed as an SCI wake-up event. The

power button status register is AcpiPmEvtBlk, bit[8]. The BIOS must make sure this bit is cleared

prior to the entry into any C or S states.

In addition, when the power button is pressed for 4 seconds, the SB600 will shut down the entire

system (by going to S5). No programming is required for this function.

8.5 C-State Break Events

8.5.1 Break Events for C2 State

Under C2 the break events are as follows:

• PBE#

• Special_message from CPU (AMD Athlon™ mode)

• I/O write to special register (AMD Athlon mode)

• SMI#

• NMI

• INIT

• Interrupts (in PIC mode only)

8.5.2 Break Events for C3 and C4 States

All of the events listed (above) as break events in C2 state are also break events in C3 and C4

states. In addition, the Bus Master Status is also a break event in C3 and C4 states.

8.6 Save/Restore Sequence for S3 State

8.6.1 Register Save Sequence for S3 State

Prior to initiating S3 states, the BIOS must save the registers on the machine. The BIOS reserves

a section of the memory and a section of the CMOS to save the registers. Depending on the BIOS

architecture, these registers may be saved either one time just prior to handing of the control over

to the OS, or every time just before going into the S3 states.

The following registers must be saved:

• Some Northbridge registers in CMOS

• Some Northbridge and Memory Controller registers

• Southbridge PCI registers on the SB600

• Southbridge non-PCI registers

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AMD SB600 Specifications Page 34