AMD SB600 Specifications Page 3

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©
2008 Advanced Micro Devices Inc.
Table of Contents
AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary
Page 3
Table of Contents
1 Introduction .................................................................................................................7
1.1 About This Manual........................................................................................................................7
1.2 Overview.......................................................................................................................................7
1.3 PCI Internal Devices ...................................................................................................................10
2 SB600 Programming Architecture..........................................................................12
2.1 PCI Devices and Functions .........................................................................................................12
2.2 I/O Map .......................................................................................................................................13
2.2.1 Fixed I/O Address Ranges...................................................................................................................13
2.2.1.1 Fixed I/O Address Ranges – SB600 Proprietary Ports................................................................13
2.2.2 Variable I/O Decode Ranges ...............................................................................................................13
2.3 Memory Map...............................................................................................................................14
3 SB600 Early-POST Initialization.............................................................................15
3.1 512K/1M ROM Enable...............................................................................................................15
3.1.1 PCI ROM.............................................................................................................................................15
3.1.2 LPC ROM............................................................................................................................................15
3.1.3 LPC ROM Read/Write Protect ............................................................................................................15
3.1.4 SPI ROM controller.............................................................................................................................16
3.2 Real Time Clock (RTC) ..............................................................................................................17
3.2.1 RTC Access .........................................................................................................................................17
3.2.1.1 Special Locked Area in CMOS ...................................................................................................17
3.2.1.2 Century Byte................................................................................................................................17
3.2.1.3 Date Alarm...................................................................................................................................17
3.3 BIOS RAM..................................................................................................................................18
3.4 Serial IRQ....................................................................................................................................18
3.5 SubSystemID and SubSystem Vendor ID...................................................................................19
3.6 AMD Athlon™ Processor Registers ...........................................................................................19
3.7 System Restart after Power Fail ..................................................................................................20
3.7.1 Power Fail and Alarm Setup................................................................................................................20
4 PCI IRQ Routing.......................................................................................................21
4.1 PCI IRQ Routing Registers.........................................................................................................21
4.2 PCI IRQ BIOS Programming......................................................................................................21
4.3 Integrated PCI Devices IRQ Routing..........................................................................................22
4.3.1 IRQ Routing for HD Audio.................................................................................................................22
4.4 PCI IRQ Routing for APIC Mode...............................................................................................23
5 SMBus Programming ...............................................................................................24
5.1 SMBus I/O Base Address............................................................................................................24
5.2 SMBus Timing............................................................................................................................24
5.3 SMBus Host Controller Programming........................................................................................25
6 IDE Controller...........................................................................................................27
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