AMD SB600 Specifications download pdf (Page 15)

2008 Advanced Micro Devices Inc.

SB600 Early-POST Initialization

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 15

3 SB600 Early-POST Initialization

The system BIOS needs to configure the SB600 at the very beginning of POST. Some of the

settings will change depending on the OEM design, or on the newer revision chipset.

3.1 512K/1M ROM Enable

With the SB600 design, there can be two possible ROM sources: PCI ROM and LPC ROM. Two

pin straps (UseLpcRom, FWHDisable) decide where the ROM is (see the SB600 databook).

Upon system power on, the SB600 enables 256K ROM by default. The BIOS needs to enable

512K ROM or up to 1M for LPC ROM, if required.

3.1.1 PCI ROM

Control Bit Description

256K ROM

(Default)

512K ROM

Setting

SMBus PCI Reg41h[Bit1] When set to 1, the address between FFF80000h to

FFFDFFFFh will be directed to the PCI ROM

interface.

0 1

SMBus PCI Reg41h[Bit4] When set to 1, the address between 0E0000h to

0EFFFFh will be directed to the PCI ROM

interface.

0 1

3.1.2 LPC ROM

To use the LPC ROM, the pin straps UseLpcRom, FWHDisable must be set accordingly.

Control Bit(s) Description Default

512K ROM

Setting

1 M ROM

Setting

LPC PCI

Reg68h

16-bit starting & end address of the

LPC ROM memory address range 1.

000E0000h 000E0000h 000E0000h

LPC PCI Reg6Ch 16-bit starting & end address of the

LPC ROM memory address range 2.

FFFE0000

FFF80000h FFF00000h

LPC PCI

Reg48Hh[Bits4:3

]

Enable bits for LPC ROM memory

address range 1 & 2.

Note: with pins straps set to LPC

ROM, these two bits have no effect on

Reg68 & Reg6C.

00b 11b 11b

3.1.3 LPC ROM Read/Write Protect

The SB600 allows all or a portion of the LPC ROM addressed by the firmware hub to be read

protected, write protected, or both read and write protected. Four dword registers are provided to

select up to 4 LPC ROM ranges for read or write protection. The ROM protection range is

defined by the base address and the length. The base address is aligned at a 2K boundary. The

address length can be from 1K to 256K in increments of 1K.

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AMD SB600 Specifications Page 15

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