AMD SB600 Specifications download pdf (Page 38)

2008 Advanced Micro Devices Inc.

APIC Programming

AMD SB600 BIOS Developer’s Guide (Public Version) Proprietary

Page 38

9.5 APIC IRQ Routing

During the BIOS POST, the BIOS will do normal PCI IRQ routing through port C00h/C01h.

Once APIC is fully enabled by the OS, the routing in C00h/C01 must be all cleared to zero.

The following is a sample ASL code that may be incorporated into the BIOS:

Name(PICF,0x00)

Method(_PIC, 0x01, NotSerialized)

{

Store (Arg0, PICF)

If(Arg0) {

\_SB.PCI0.LPC0.DSPI() // clear interrupt at 0xC00/0xC01

}

OperationRegion(PIRQ, SystemIO, 0xC00, 0x2)

Field(PIRQ, ByteAcc, NoLock, Preserve)

{

PIID, 8,

PIDA, 8

}

IndexField(PIID, PIDA, ByteAcc, NoLock, Preserve)

{

PIRA, 8,

PIRB, 8,

PIRC, 8,

PIRD, 8,

PIRS, 8

Offset(0x09),

PIRE, 8,

PIRF, 8,

PIRG, 8,

PIRH, 8

}

Method(DSPI)

{

Store(0x00, PIRA)

Store(0x00, PIRB)

Store(0x00, PIRC)

Store(0x00, PIRD)

Store(0x00, PIRS)

Store(0x00, PIRE)

Store(0x00, PIRF)

Store(0x00, PIRG)

Store(0x00, PIRH)

}

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AMD SB600 Specifications Page 38

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